1. Technical Field
The present invention relates to a test apparatus, a test vector generating unit, a test method, a program, and a recording medium. In particular, the present invention relates to a test apparatus that tests a device under test such as a semiconductor circuit.
2. Related Art
A conventional method for testing a device under test such as a semiconductor circuit involves measuring a characteristic of the device under test while a logic circuit of the device under test operates according to a prescribed logic pattern. If the device under test includes a CMOS circuit, the device under test is tested by measuring the quiescent current IDDQ or the transient current IDDT flowing to the device under test while changing the logic pattern applied to the CMOS circuit, as in, for example, “IDDX-Based Test Methods: A Survey”, SAGAR S. SABADE and DUNCAN M. WALKER, ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 2, April 2004, Pages 159-198.
Since one of a pair of transistors in the gate is turned off, the current flowing from the H power supply line to the L power supply line via the CMOS circuit is extremely small. If these transistors are defective, a relatively large leak current might flow through the CMOS circuit depending on the logic state of the CMOS circuit.
This leak current can be detected by observing the quiescent current IDDQ flowing to the device under test. The defective portion of the device under test can be estimated by analyzing test vectors applied to the device under test while a relatively large leak current flows to the device under test.
A certain fluctuation of IDDQ is expected. But if the fluctuation of the IDDQ current exceeds a prescribed value, the device is considered defective.
Since measuring the quiescent current IDDQ involves detecting the current corresponding to the leak current of the CMOS circuit, it is necessary to measure the current with a high degree of accuracy. However, the quiescent current IDDQ flowing to the device under test might change depending on the test vectors.
FIG. 12A shows an exemplary circuit in a device under test 312. The device under test 312 uses CMOS circuits for each of a 2-input AND gate 302, a 2-input OR gate 304, and a 2-input OR gate 306 included therein. The AND gate 302 outputs an AND of an input bit i2 and an input bit i3. The OR gate 304 outputs an OR of the input bit i1 and an output bit of the AND gate 302. The OR gate 306 outputs an OR of an input bit i3 and an input bit i4.
FIG. 12B is a table showing the leak current in the non-defective AND gate 302, OR gate 304, and OR gate 306, for each input logic state. For example, when the device under test 312 is supplied with the input bits {i1, i2, i3, i4}={0, 1, 1, 0}, the leak current of the AND gate 302 is 16 pA, the leak current of the OR gate 304 is 13 pA, and the leak current of the OR gate 306 is 11 pA. Therefore, the leak current of the device under test 312 is 16 pA+13 pA+11 pA=40 pA.
On the other hand, when the device under test 312 is supplied with the input bits {i1, i2, i3, i4}={1, 0, 0, 1}, the leak current of the AND gate 302 is 8 pA, the leak current of the OR gate 304 is 11 pA, and the leak current of the OR gate 306 is 13 pA. Therefore, the leak current of the device under test 312 is 8 pA+11 pA+13 pA=32 pA.
In this way, the leak current in the device under test 312 changes according to the pattern of the input bits. When the leak current changes depending on the input pattern, it becomes difficult to accurately detect the fluctuation of the leak current caused by a defect. Therefore, pass/fail of the device under test 312 cannot be accurately judged.